Method and device for generating a clock signal that is coupled to a reference signal

ABSTRACT

In order to generate a clock signal (f T1 ) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (f T1 ) is generated from a high-frequency clock pulse (f 0 ) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (f T1 ) is generated from the high-frequency clock pulse (f 0 ) and the phase deviation between the first clock pulse (f T2 ) and the second clock pulse (f T1 ) is determined. The digitized sampling values of the reference signal (FBAS) at the first clock frequency (f T1 ) are converted, according to the phase deviation determined, into corresponding digitized sampling values having the second clock frequency (f T1 ) and are used as a target specification for generating the second clock pulse (f T1 ) thus coupled to the reference signal.

BACKGROUND OF THE INVENTION

The invention relates to the field of generating a clock signal fordigital systems, and in particular to a system for generating aline-coupled or color-carrier-coupled system clock signal for decoding avideo signal.

In most integrated circuits (ICs) for video processing, especially inthe area of digital television, a line-coupled or color-carrier-coupledclock signal is required which is coupled to the analog video signal(e.g., FBAS signal), and thus synchronized with this signal. Inprinciple, two different couplings are possible—line coupling or colorcarrier coupling. In the first case, the horizontal sync pulses of thevideo signal are used as the reference for clocking, while in the secondcase, the color burst of the video signal is used.

Two different approaches are used to achieve the above-referencedcoupling. In the first approach, the system clock provided for therespective IC is re-adjusted based on the synchronization signalscontained in the FBAS signal. The analog-to-digital converter typicallyprovided to digitize the FBAS signal is operated at the same systemclock.

With the second system clock, the respective system, and thus theanalog-to-digital converter, are free so that the FBAS signal is sampledasynchronously by the analog-to-digital converter. A digital circuitcalculates the deviation between the actual sampling frequency and thevirtual sampling frequency coupled to the FBAS signal (so-called skewvalue), and then corrects the asynchronous sampling values of thedigitized FBAS signal.

Due to large-scale integration (e.g., “system on a chip”), it isnecessary to accommodate both of the above methods on one IC since eachmethod has advantages for specific system components. However, to useboth methods simultaneously, the analog FBAS signal would have to beanalog-to-digital-converted twice. The first analog-to-digitalconversion is implemented using a free-running clock, that is, with anasynchronous clock signal not coupled to the FBAS signal. The secondanalog-to-digital conversion is implemented with a coupled and regulatedclock signal. Due to its overall complexity, however, this approach isnot feasible.

Increasingly, there are applications in which signals digitized atanother location, such as FBAS signals or other signals, are alreadycoupled with a clock. Such applications are found, for example, inpersonal computers in which the system clock is generally fixed andwhich determine the digitization and data sequence by predeterminedprocessing groups.

There is a need for a system and method for generating a clock signalthat is coupled to a reference signal.

SUMMARY OF THE INVENTION

A free-running clock signal and a clock signal coupled to a referencesignal are derived from the same (high-frequency and quartz-coupled)clock signal. The resulting pre-knowledge of the phase position of thedifferent clock signals relative to each other may be used to calculateor convert the digitized sampling values of an analog-to-digitalconverter, operated at the free-running asynchronous clock frequency, todigitized sampling values corresponding to the coupled clock signal. Thedigital sampling values in turn form the basis for generating orregulating the coupled clock signal.

Advantageously, only a single analog-to-digital converter is required.

A digital phase-locked loop with a digitally-controlled oscillator(“digital timing oscillator,” DTO) may, for example, be used to controlthe coupled clock signal. As a result, analog components, which aretechnology-dependent and difficult to test, are eliminated in thecontrol circuit. Of course, other systems such as delay lines, etcetera, to output the coupled clock signal are also conceivable.

The conversion of the free-running clock signal of the digital samplingvalues with the free-running clock frequency from the analog-to-digitalconverter to corresponding sampling values with the coupled clockfrequency may be performed by linear interpolation. The linearinterpolation is implemented based upon the determined phase position orphase deviation between the free-running clock signal and the coupledclock signal. The sampling values of the analog-to-digital converterrequired for interpolation are stored simultaneously with the phasevalue determined each time in agreement with the coupled clock signal,and fed to a corresponding interpolator.

The invention may be used to generate a clock signal coupled to atelevision or video signal in the field of digital television. However,the invention is not restricted to this preferred application but may beutilized anywhere there is a need to generate a clock signal coupled toa reference clock signal.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of preferred embodiments thereof, as illustrated in theaccompanying drawing.

BRIEF DESCRIPTION OF THE DRAWING

The FIGURE illustrates a block diagram of system for generating a clocksignal coupled to a reference signal.

DETAILED DESCRIPTION OF THE INVENTION

With integrated circuits for video processing such as those used indigital television receivers, it is often necessary to couple theinternal clock signals with the received analog video signal (e.g., FBASsignal). In principle, line coupling or a color carrier coupling arepossible. In the first case, the horizontal sync pulses of the videosignal are used as the reference for clock generation, while in thesecond case, the so-called color burst of the video signal is used. Thefollowing approach assumes that coupling with the horizontal sync pulsesof the received video signal is implemented. However, the technique ofthe present invention is also applicable to color carrier coupling.

An analog FBAS signal on a line 12 is sampled by an analog-to-digitalconverter 14 driven by a free-running clock frequency f_(T2) on a line16, to provide a digital FBAS signal on a line 18. This sampling isrequired for the downstream digital color decoding.

The free-running clock frequency f_(T2) on the line 16 is obtained bydividing a free-running high-frequency and quartz-coupled clock signalhaving a frequency f₀ of at least 600 MHz. The high frequency f₀ ensuresthe phase resolution 1/f₀<3 ns required for 100 Hz television receivers.In this case, f₀=648 MHz.

In this case, the free-running clock frequency is f_(T2)=20.25 MHz. Adivider 20 monitors the state change of the most significant bit (MSB)of a data word generated by a 5-bit counter 22 that is driven by ahigh-frequency clock frequency f₀ on a line 24. The output of thedivider 20 on a line 26 is provided to a register 28 that is alsoclocked at the frequency f₀. As a result, the free-running clock signalf_(T2) on the line 16 is equal to f₀/2⁵, that is 20.25 MHz when f₀=648MHz.

In a digital 100 Hz television receiver, the image must be displayedline-coupled at 36 MHz at the output after a corresponding 100 Hzconversion. To generate this line-coupled clock frequency f_(T1), adigital phase-locked loop is used together with a digital phase detectorand loop filter 30, and a digitally controlled oscillator 32, incombination with an interpolator 34. The digital phase detector and loopfilter 30 is operated at the coupled clock frequency f_(T1) anddetermines the phase deviation between the horizontal sync pulsescontained in the FBAS signal and the clock signals momentarily generatedby the digitally controlled oscillator 32 which are output as thecoupled clock signal f_(T1). The phase deviation is converted to anincremental value INCR on a line 36 for the digitally controlledoscillator 32 operated at the clock frequency f₀ so that in the adjustedstate of the digitally controlled oscillator 32 an output frequencyf_(T1) on the line 38 is generated which is matched to the horizontalfrequency of the FBAS signal and coupled to it.

Based on the fixed connection between the free-running clock frequencyf_(T2) and the coupled clock frequency f_(T1) via the high-frequencyquartz clock frequency f₀, the phase position between these two clockfrequencies may easily be tracked with a resolution of 1/f₀.

The count of the 5-bit counter 22 provides the momentary phase offree-running clock frequency f_(T2) (20.25 MHz). If the momentary countof the counter 22 is stored with each active clock-pulse edge of coupledclock frequency f_(T1) (36 MHz) in a register 40, this stored value maybe used directly to convert the 20.25 MHz sampling values to thecorresponding 36 MHz sampling values, since each value stored in theregister 40 is a measure of the phase deviation between the coupledclock signal f_(T1) (36 MHz) and the free-running clock signal f_(T2)(20.25 MHz).

For this purpose, the interpolator 34 is provided, already mentioned andoperated at the coupled clock frequency f_(T1), to which the respectivecount stored in register 10 is fed. In the embodiment shown, theinterpolator 34 performs a linear interpolation which is sufficient forthe considered case of sync recognition. The measurement of two samplingvalues of the digital FBAS signal provided by the analog-to-digitalconverter 14 at free-running clock frequency f_(T2) is sufficient forthe linear interpolation. For this reason, two registers 42 and 44operated at free-running clock frequency f_(T2) follow theanalog-to-digital converter 14 and store two successive sampling valuesfor the digital FBAS signal. To provide these sampling values to theinterpolator 34, the sampling values are stored simultaneously alongwith the phase value stored in the register 40. This task is performedby the registers 46 and 48 operated at the coupled clock frequencyf_(T1) in which one sampling value each is thus stored from the 20.25MHz system synchronously with the register 40.

In the event the interpolator 34 is to be used to perform not just alinear interpolation but a more-significant interpolation requiring morethan two sampling values of the digital FBAS signal, the number ofregisters operated at the free-running clock frequency f_(T2), as wellas the number of registers operated at the coupled clock frequencyf_(T1), must be increased.

Based on the interpolation of the FBAS signal sampled at free-runningfrequency f_(T2), the interpolator 34 determines new digital samplingvalues for the coupled clock frequency f_(T1). The digital FBAS datastream thus obtained at frequency f_(T1) then serves as the input signalfor the digital phase-locked loop, with the result that the line-coupledclock frequency f_(T1) is finally generated by the digitally controlledoscillator 32 which may be in the form of a closed-loop-controlledadder.

Although the present invention has been shown and described with respectto several preferred embodiments thereof, various changes, omissions andadditions to the form and detail thereof, may be made therein, withoutdeparting from the spirit and scope of the invention.

1. A method for generating a clock signal coupled to a reference signal,comprising the steps: a) supplying an operating clock signal (f₀); b)supplying a first clock signal (f_(T2)); c) supplying a sequence ofsampling values of the reference signal at the frequency of the firstclock signal (f_(T2)); d) supplying a second clock signal (f_(T1)); e)determining the phase deviation between the first clock signal (f_(T2))and the second clock signal (f_(T1)); and f) converting the samplingvalues of the reference signal with the frequency of the first clocksignal (f_(T2)) to corresponding sampling values with the frequency ofthe second clock signal (f_(T1)), the conversion being based on thephase deviation determined in step e), where the resulting samplingvalues of the reference signal are used in step d) as the targetspecification to generate the second clock signal (f_(T1)) coupled withthe reference signal.
 2. The method of claim 1, where the first clocksignal (f_(T2)) and/or the second clock signal (f_(T1)) is generatedfrom the operating clock signal (f₀).
 3. The method of claim 1, wherethe reference signal is coupled to the first clock signal (f_(T2)) orthe second clock signal (f_(T1)), and the first clock signal (f_(T2)) orthe second clock signal (f_(T1)) is generated from the reference signal.4. The method of claim 1, where the first clock signal (f_(T2)) and/orthe second clock signal (f_(T1)) is generated from an externallysupplied clock signal.
 5. The method of claim 4, where the samplingvalues are generated as digitized sampling values.
 6. The method ofclaim 5, where in step f) an interpolation is performed on the samplingvalues, provided in step c), of the reference signal at the frequency ofthe first clock signal (f_(T2)), and on the basis of the phase deviationdetermined in step e), where the interpolated digitized sampling valuesof the reference signal (FBAS) thus obtained are used in step d) as thetarget specification to generate the second clock signal (f_(T1)). 7.The method of claim 1, where a linear interpolation is performed in stepf).
 8. The method of claim 1, where the second clock signal (f_(T1)) isgenerated in step d) with the aid of a digital phase-locked loop.
 9. Themethod of claim 6, where a high-frequency quartz-coupled clock signal isused as the operating clock signal (f₀).
 10. The method of claim 6,where the sampling values of the reference signal supplied in step c)are stored at the frequency of the second clock signal (f_(T1)) beforetheir use in the conversion effected in step f), and are subsequentlyused only for the conversion.
 11. The method of claim 10, where in stepe) the phase deviation between the first clock signal (f_(T2)) and thesecond clock signal (f_(T1)) is determined at the frequency of thesecond clock signal (f_(T1)), and stored synchronously with thedigitized sampling values of the reference signal.
 12. The method ofclaim 1, where in step b) the first clock signal (f_(T2)) is generatedby evaluating the count of a counter operated with the operating clocksignal (f₀).
 13. The method of claim 12, where the momentary count ofthe counter is determined at the frequency of the second clock signal(f_(T1)), and the count determined each time is used in step e) as themeasure of the phase deviation between the first clock signal (f_(T2))and the second clock signal (f_(T1)).
 14. A device for generating aclock signal coupled to a reference signal, comprising: a firstclock-signal generating device to generate a first clock signal(f_(T2)); a sampling device operated with the first clock signal(f_(T2)) which generates a sequence of sampling values for the referencesignal; a second clock-signal generating device to generate a secondclock signal (f_(T1)); a phase-deviation determination device todetermine the phase deviation between the first clock signal (f_(T2))and the second clock signal (f_(T1)), and a conversion device to convertthe sampling values of the reference signal with the frequency of thefirst clock signal (f_(T2)) to the corresponding sampling values withthe frequency of the second clock signal (f_(T1)), the conversion beingbased on the phase deviation determined by the phase-deviationdetermination device, wherein the sampling values of the referencesignal output by the conversion device are supplied to the secondclock-signal generating device as the target specification forgenerating the second clock signal (f_(T1)), so that the second clocksignal (f_(T1)) is output by the second clock-signal generating devicecoupled to the reference signal.
 15. The device of claim 14, where thefirst clock-signal generating device generates the first clock signal(f_(T2)) and/or the second clock signal (f_(T1)) from the operatingclock signal (f₀).
 16. The device of claim 14, where the firstclock-signal generating device generates the first clock signal (f_(T2))or the second clock signal (f_(T1)) from the reference signal.
 17. Thedevice of claim 14, where the first clock-signal generating devicegenerates the first clock signal (f_(T2)) and/or the second clock signal(f_(T1)) from an externally supplied clock signal that specificallycorresponds to the first clock signal (f_(T2)).
 18. The device of claim14, in which the sampling device comprises an analog-to-digitalconverter.
 19. The device of claim 14, where the conversion deviceoutputs digitized sampling values.
 20. The device of claim 14, where theconversion device comprises a linear interpolator.
 21. The device ofclaim 14, where the second clock-signal generating device comprises adigital phase-locked loop that includes a digital phase detector deviceand a digitally controlled oscillator device, where the digitallycontrolled oscillator device generates the second clock signal (f_(T1)),and the digital phase detector device determines the phase deviationbetween the digitized sampling values of the reference signal output bythe conversion device and the second clock signal (f_(T1)) and,depending thereon, generates a digital incremental value (INCR) for thedigitally controlled oscillator device by which to adjust the frequencyof the second clock signal (f_(T1)).
 22. The device of claim 14, wherethe operating clock signal (f₀) comprises a high-frequencyquartz-coupled clock signal.
 23. The device of claim 14, comprisingfirst memory means for storing the sampling values of the referencesignal with the frequency of the second clock signal (f_(T1)) output bythe analog-to-digital converter, and second memory means for storing thedigital sampling values with the frequency of the first clock signal(f_(T2)) stored in the first memory means, and to feed the samplingvalues to the conversion device.
 24. The device of claim 14, comprisinga counter operated at the operating clock frequency (f₀), and the firstclock-signal generating device is designed so that the first clocksignal (f_(T2)) is generated by evaluating the count of the counter. 25.The device of claim 24, where the phase-deviation determination devicecomprises memory means to determine the momentary count of the counterat the frequency of the second clock signal (f_(T1)), and to feed thecount determined each time to the conversion device as the measure ofthe phase deviation between the first clock signal (f_(T2)) and thesecond clock signal (f_(T1)).
 26. The device of claim 14, where thereference signal comprises a video signal, specifically a televisionsignal, and that the frequency (f₀) of the operating clock signal fromwhich the first and/or second clock signal (f_(T2); f_(T1)) is derivedis at least 600 MHz.